The controller supports two wishbone interfaces: a control interface and a data interface. It supports a high speed read mode via pipelined wishbone read interactions. In a similar fashion, this controller was built upon a SPI flash controller. However, because of the legacy associated with the interface, the interface defaults to SPI mode and offers only some commands in four bit mode. Thus, for certain commands, all four wires (including both MOSI and MISO lines) become unidirectional sending data to or from the device. When this proved to be not sufficiently fast enough, additional commands were added to the protocol in addition to two additional wires.
#QSPI CONTROLLER SERIAL#
Such an interface consists of four wires: a chip select, a clock, a master out slave in (MOSI) serial line, and a master in slave out (MISO) serial line. Indeed, reading from this memory is as simple as reading from the wishbone!įor those not familiar with a Quad-SPI flash, the basic device is built upon a SPI interface. The controller hides much, although not all, of the flash chip interactions from the user behind wishbone read and write accesses. It currently works for me on the 4MB Spansion flash found within a Basys-3 development board. If you fail to enable the User mode SPI support then the SPI device files will not be created.Įdit the file subsystems/linux/configs/device-tree/system-top.dts in your PetaLinux project directory, then add the following lines.This is a Quad-SPI Flash controller.
#QSPI CONTROLLER DRIVER#
Navigate to Device Drivers-> SPI support and make sure that Cadence SPI controller, Xilinx SPI controller command module, Xilinx Zynq QSPI controller, and User mode SPI device driver support are all enabled. To configure the kernel run the following command. Then you need to enable SPI support for your kernel. The first step after creating your project is to use petalinux-config to read the hardware description that you exported from Vivado. This step is critical: without it, Linux won’t create the SPI device file to control your device. Before you build PetaLinux, though, you need to modify the device tree to create the appropriate device file for your SPI device. You need to create a PetaLinux project and extract the hardware description from your project SDK directory as discussed in tutorial 23. These steps are covered in other tutorials, so I won’t go into details here. Generate a bitstream and export your design to SDK. Now synthesize the design and use the I/O Planner to place the outputs where you want on your FPGA.
#QSPI CONTROLLER SOFTWARE#
This can be really useful for debugging your software using the embedded logic analyzer feature of Vivado. Note that I have also marked the pins for debug. Don’t worry about not having those in your design. On my FPGA, I also connect to a DS3231 realtime clock over I2C and have some GPIOs connected as well. Wire that to the SPI0_SS_I pin on the ARM processor. To do this, instantiate a constant IP module and set the value to 1. Also, the SPI0_SS_I pin must be connected to a logic 1 value due to a bug in the toolchain. Note: there will be many unused pins, since the controller can be used as a master, slave, or both. Wire them up to the corresponding pin on the SPI controller. In my case I am connecting to a MAX 5216 DAC which does not have read capability so I only have three output pins which I call MAX5216_SCLK, MAX5216_MOSI, and MAX5216_SSN. If you wish to read from the SPI device, you’ll also need a data input. For a SPI master, you’ll need at least one chip select output, one clock output, and probably a data output to write to the SPI device. Next, you’re going to need to make ports on the FPGA which will connect to the SPI controller. This programs the SPI control signals to use the Programmable Logic rather than pins dedicated to the Processor Subsystem. In the IO column make sure that EMIO is selected. Expand the I/O Peripherals section and scroll down to SPI 0. Next, go to the MIO Configuration section of the Page Navigator. Click on the Peripheral I/O Pins section of the Page Navigator and check the box next to SPI 0. Note that Quad SPI or QSPI is unrelated to this discussion. This will bring up the IP configuration window. Double-click on the ZYNQ processing subsystem in your Block Design in the IP Integrator window. Enabling the SPI controllerįirst you need to enable the SPI controller on the ZYNQ subsystem. For this tutorial I am using Vivado 2016.2 and PetaLinux 2016.2. In this tutorial, we’ll do things the “official” way, and use the one of the hard IP SPI controllers present on the ZYNQ chip. In T utorial 24, I covered controlling a SPI device by just taking control of the memory mapped GPIO and bit-banging the SPI without a driver.